september 2001 2001 fairchild semiconductor corporation fd n340p rev e (w) fdn340p single p - channel , logic level , powertrench mosfet general description this p - channel logic level mosfet is produced using fairchild semiconductor advanced power trench process that has been especially tailored to minimize the on - state resistance and yet maintain low gate charge for superior switching performance. these devices are well suited for portable electronics applications: l oad switching and power management, battery charging circuits, and dc/dc conversion. feature s ? 2a, 20 v r ds(on) = 7 0 m w @ v gs = ? 4.5 v r ds(on) = 11 0 m w @ v gs = ? 2.5 v low gate charge (7.2 nc typical). high performance trench technology for extremely low r ds(on) . high power version of industry standard sot - 23 package . identical pin - out to sot - 23 with 30% higher power handling ca pability. g d s supersot -3 tm 340 d s g absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter ratings units v dss drain - source voltage ? 20 v v gss gate - source voltage 8 v i d drain current ? continuous (note 1a) ? 2 a ? pulsed ? 10 po wer dissipation for single operation (note 1a) 0 .5 p d (note 1b) 0.46 w t j , t stg operating and storage junction temperature range ? 55 to +150 c thermal characteristics r q ja thermal resistance, junction - to - ambient (note 1a) 2 50 c/w r q jc thermal resistance, junction - to - case (note 1) 7 5 c/w package marking and ordering information device marking device reel size tape width quantity 340 fdn340p 7?? 8mm 3000 units fdn340p
fd n340p rev e (w) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain ? source breakdown voltage v gs = 0 v, i d = ? 250 m a ? 20 v d bv dss d t j breakdown voltage temperature coefficient i d = ? 250 m a,referenced to 25 c ? 1 2 mv/ c v ds = ? 16 v, v gs = 0 v ? 1 m a i dss zero gate voltage drain current v ds = ? 16 v, v gs = 0 v, t j = 5 5 c ? 10 i gssf gate ? body leakage, forward v gs = 8 v, v ds = 0 v 100 na i gssr gate ? body leakage, reverse v gs = ? 8 v , v ds = 0 v ? 100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = ? 250 m a ? 0.4 ? 0. 8 ? 1 .5 v d v gs(th) d t j gate threshold voltage temperature coeff icient i d = ? 250 m a,referenced to 25 c 3 mv/ c v gs = ? 4.5 v, i d = ? 2 a 60 7 0 w v gs = ? 4.5 v, i d = ? 2 a, t j =125 c 77 1 20 r ds(on) static drain ? source on ? resistance v gs = ? 2.5 v, i d = ? 1.7a, 82 11 0 i d(on) on ? state drain current v gs = ? 4.5 v, v ds = ? 5 v ? 5 a g fs forward transconductance v ds = ? 4. 5 v, i d = ? 2 a 9 s dynamic char acteristics 600 input capacitance 779 pf 175 output capacitance 121 pf 80 reverse transfer capacitance v ds = ? 10 v, v gs = 0 v, f = 1.0 mhz 56 pf switching characteristics (note 2) t d(on) turn ? on delay time 10 20 ns t r turn ? on rise time 9 10 ns t d(off) turn ? off delay time 27 43 ns t f turn ? off fall time v dd = ? 10 v, i d = ? 1 a, v gs = ? 4.5 v, r gen = 6 w 11 20 ns q g total gate charge 7.2 10 nc q gs gate ? source charge 1.7 nc q gd gate ? drain charge v ds = ? 10 v, i d = ? 3.5 a, v gs = ? 4.5 v 1.5 nc drain ? source diode characteristics and maximum ratings i s maximum continuous drain ? source diode forward current ? 0.4 2 a v sd drain ? source diode forwa rd voltage v gs = 0 v, i s = ? 0.4 2 a (note 2 ) ? 0.7 ? 1.2 v notes: 1. r q ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. a. 250c/w when mounted on a 0.02in 2 pad of 2 oz copper b. 270c/w when mounted on a .001 in 2 pad of 2 oz copper scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 m s, duty cycle < 2.0% fdn340p
fd n340p rev e (w) typical characteristics 0 3 6 9 12 15 0 1 2 3 4 -v ds , drain to source voltage (v) -i d , drain current (a) v gs = -4.5v -3.5v -3.0v -1.5v -2.0v -2.5v v 0.8 1 1.2 1.4 1.6 1.8 2 0 3 6 9 12 15 -i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs =-2.0v -3.0v -2.5v -3.5v -4.5v figure 1. on - region characteristics. figure 2. on - resistance variation with drain current and gate voltage. 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = -2a v gs = -4.5v 0.02 0.06 0.1 0.14 0.18 0.22 1 2 3 4 5 -v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = -1a t a = 125 o c t a = 25 o c figure 3. on - resistance variation with temperature. figure 4. on - resistance variation with gate - to - source voltage. 0 2 4 6 8 10 0.5 1 1.5 2 2.5 -v gs , gate to source voltage (v) -i d , drain current (a) t a = -55 o c 25 o c 125 o c v ds = -5v 0.0001 0.001 0.01 0.1 1 10 0 0.2 0.4 0.6 0.8 1 1.2 -v sd , body diode forward voltage (v) -i s , reverse drain current (a) v gs = 0v t a = 125 o c 25 o c -55 o c figure 5. transfer characteristics. fi gure 6. body diode forward voltage variation with source current and temperature. fdn340p
fd n340p rev e (w) typical characteristics 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = -3.5a v ds = -5v -10v -15v 0 200 400 600 800 1000 0 5 10 15 20 -v ds , drain to source voltage (v) capacitance (pf) c iss c oss c rss f = 1 mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capa citance characteristics. 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-source voltage (v) -i d , drain current (a) dc 1s 100ms 100 m s r ds(on) limit v gs = -10v single pulse r q ja = 270 o c/w t a = 25 o c 10ms 1ms 0.001 0.01 0.1 1 10 100 0 10 20 30 40 50 single pulse time (sec) power (w) single pulse r = 270 c/w t = 25c q ja a figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r (t) = r(t) * r r = 270 c/w duty cycle, d = t /t 1 2 q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 figure 11. transient thermal response curve. thermal char acterization performed using the conditions described in note 1 b . transient thermal response will change depending on the circuit board design. fdn340p
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